1. Field of the Invention
The invention generally relates to silicide formation processes, and, more particularly, to a structure and method for simultaneously tuning silicide stress and controlling silicon bridging during a self-aligned silicide formation process.
2. Description of the Related Art
As complementary metal oxide semiconductor devices are scaled and, particularly, as channel lengths are scaled, parasitic resistance in such devices increases. To minimize parasitic resistance, silicide regions are formed on polysilicon gate conductors, on silicon source/drain diffusion areas and also as a local interconnects between devices (e.g., between a silicon source/drain diffusion area of one device and the polysilicon gate conductor of another device). These silicide regions provide low resistance and are able to withstand high temperatures. Thus, they can be used to improve CMOS device speed and, therefore, performance.
During a conventional self-aligned silicide formation process, a metal layer (e.g., a 6-10 nm nickel, titanium or cobalt layer) is deposited over a device structure (e.g., over a field effect transistor formed on a semiconductor wafer such as a silicon-on-insulator (SOI) wafer). Specifically, the metal layer can be deposited over the silicon source/drain diffusion areas, over the polysilicon gate conductor and over the sidewall spacers that are adjacent to the gate conductor. This step is followed by the deposition of a protective cap layer (e.g., titanium nitride) that prevents contamination of the metal layer during subsequent thermal anneals. A first anneal is applied to form silicide regions at the silicon-metal interfaces, including the polysilicon-metal interfaces, in a thermal reaction that results in a significant volume change. Then, the protective cap layer and the remaining metal are removed. A second thermal anneal can be applied to transform any silicides in metal rich phases into monosilicides.
Several factors should be considered during the silicide formation process to ensure optimal CMOS device performance. First, the process should avoid bridging of silicon into unwanted areas to prevent shorts. For example, since there is a significant volume change when metal thermally reacts with silicon to form metal silicide, a protective cap layer with limited flexibility may allow voids to open up to compensate for the volume changes. Such voids can allow silicon to move or bridge into unwanted areas of the device (e.g., over sidewall spacers) and, thus, potentially impair device performance. Second, CMOS device performance can be optimized by tuning the tensile or compressive stress of the silicide regions as they are formed. For example, a more tensile silicide will place the silicon or polysilicon underlayers in compression and, thus, in a better state for n-type field effect transistor (n-FET) performance. Alternatively, a more compressive silicide will place the silicon or polysilicon underlayers in tension and, thus, in a better state for p-FET performance. Consequently, there is a need for a structure and method for simultaneously controlling silicon bridging and tuning silicide stress during a self-aligned silicide formation process.